The present invention relates to systems and methods for performing NPICD for step-down switching regulators.
Discontinuous operation occurs in circumstances of light load when using a non-synchronous buck regulator. In the case of a synchronous BUCK regulator, optimizing the efficiency of the regulator, with light load requires turning off the Low Side FET for a portion of the switching cycle. In this circumstance, the LOW SIDE FET is disabled for one switching cycle after the cycle in which the inductor current has reversed direction or has zero volts across the inductor prior to turning on the High Side FET. Turning off the LOW SIDE FET in this circumstance improves the light load efficiency by preventing needless discharge of the output capacitor and by reducing the switching losses due to turning on and off the NFET. Determination is made during the time the Low Side FET is off and prior to the turn on of the High Side FET, by sensing the voltage polarity across the Low Side Body diode. Ideally the LOW SIDE FET is shut off and held off (for the remainder of the switching cycle) when the inductor current reverses. However with light loads, there are still significant efficiency benefits, if the low side FET is held off for the entirety of the switching cycle (as opposed to only a portion of the switching cycle). In this case the BUCK regulator is operating non-synchronously.
FIG. 1 shows a conventional implementation for turning off the Low side FET, represented by “NFET” 14, in the circumstance when negative current in the inductor is present. Negative inductor current is defined as current flowing from the inductor into either the high or low side power transistors. FET 18 is a pull up and is connected between VDD and NFET 14. If negative current is not present in inductor 20 then the output of comparator 30 is LOW and flip flop (FF) 10 is SET when NFET 14 control goes HIGH. In this case, the LOW SIDE FET is turned on as both inputs to AND 12 are asserted HIGH. If after the LOW SIDE FET is on, the current in inductor 20 goes negative, comparator 30 output goes HIGH and is sent to AND 40 when NFET control is high, thus resetting FF 10 and forcing the Q output LOW, thereby shutting off the NFET 14.
In the circuit of FIG. 1, detection of negative current occurs while the LOW SIDE FET is turned on. LOW SIDE FET on resistance is typically very low (a few milliohms) for optimal efficiency. As such the voltage generated (due to negative inductor current) at the input to the comparator can be very small (in the order of a few mille volts) particularly since it is important to detect small negative currents (for optimal efficiency).
Small input voltages to the comparator are problematic in two regards: 1. Input offsets to the comparator can cause erroneous operation 2. Small overdrive typically translates to slow comparator response time. Overcoming these two issues greatly complicates the design and efficiency gain of the implementation of FIG. 1. Overcoming the offset issue forces the comparator 30 to be implemented with either large input structures or switch capacitor techniques either of which require more die area. Often a known comparator offset is introduced to swamp out the random offset. This fixed offset forces the detected negative current to be larger than would otherwise be necessary, thereby degrading the efficiency of the circuit. The small overdrive forces the current burned in the comparator 30 to be high in order to speed up the circuit. This in turn degrades the efficiency of the circuit.